A Single-Amplifier Dual-Residue Pipelined-SAR ADC

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with single open-loop residue amplifier (RA). By using the inherent characteristics of SAR conversion scheme, proposed ADC sequentially generates two levels from RA, which eliminates need for inter-stage gain-matching calibration. To convert generated residues, capacitive interpolating (I-SAR ADC) is also proposed. The I-SAR very compact because it consists one comparator, CDAC, and control logic like conventional ADC. In addition, needs no static power dissipation interpolation. A prototype fabricated in 40 nm CMOS technology occupies an active area 0.026 mm2. At sampling-rate Nyquist input, achieves SNDR (Signal-to-Noise distortion ratio) 62.1 dB 67.1 SFDR (Spurious-Free Dynamic Range), respectively. total consumed 3.9 mW under 0.9 V supply. Without any mismatch calibration, achieve Walden Figure-of-Merit (FoM) 19.0 fJ/conversion-step.